1. Field of the Invention
The present invention relates to data processing systems and, in particular, to the detection and special handling of memory-mapped Input/Output references by a pipelined microprocessor.
2. Discussion of the Prior Art
In conventional digital data processing system architecture, peripheral devices such as modems, printers or displays are accessed by a technique called memory-mapped Input/Output (I/O). According to this technique, control registers within the peripheral device are read and written by the central processing unit by executing the same instructions as those executed for reading and writing ordinary memory locations. There are, however, special characteristics associated with reading and writing certain peripheral devices that differ from the characteristics of reading and writing memory.
For example, reading a control register in a peripheral device can alter the value read on the next reference to the same register or to another register in the same device. Serial communications controllers and First-In-First-Out memories commonly operate in this manner.
Similarly, writing to a control register in a peripheral device can alter the value read from a different register. For example, in the case of National Semiconductor Corporation's NS32202 Interrupt Control Unit, before reading the counter's value from the NS32202, it is first necessary to freeze the counter's value by writing to another control register.
These special characteristics of peripheral devices cause no serious problems in data processing systems which, like currently-available microprocessors, are designed to execute instructions sequentially.
However, more complex, high performance systems execute several instructions simultaneously in a "pipelined" manner. For systems of this type, special handling procedures must be observed for I/O references to ensure that the system's programs execute correctly. For example, a pipelined computer may perform reads and writes to different memory locations in any order, but references to peripheral devices must occur in the specific order implied by the executing program.
Data processing system architectures, such as the architecture of the Hewlett-Packard Spectrum family of computers and the Digital Equipment Corporation VAX-11/750 computer, have been developed that provide for pipelined designs which detect memory-mapped I/O references and apply special handling. In these systems, a portion of the computer's memory address space is dedicated specifically for I/O, thereby restricting the location of peripheral devices to a fixed range of addresses.
While, as just stated, the issue of I/O references has been addressed in microcomputer architecture, currently available microprocessor architectures have not dedicated memory address space for I/O, or in any other manner provided for detecting memory-mapped I/O references. Consequently, it is necessary to provide an architecture to support memory-mapped I/O in microprocessor designs that are pipelined for high performance.
However, it is unacceptable for a microprocessor architecture to rely solely on the above-described method of dedicating a portion of the memory address space for I/O, because that would make the microprocessor incompatible with systems that have already been developed with peripheral devices connected at arbitrary locations.